(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of eliminating the thermal mismatch between silicon and a Printed Circuit Board substrate.
(2) Description of the Prior Art
Semiconductor device performance improvements are largely achieved by reducing device dimensions, a development that has at the same time resulted in considerable increases in device density and device complexity. These developments have resulted in placing increasing demands on the methods and techniques that are used to access the devices, also referred to as I/O capabilities of the device. This has led to new methods of packaging semiconductor devices whereby structures such as Ball Grid Array (BGA) devices and Column Grid Array (CGA) devices have been developed A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA""s are known with 40, 50 and 60 mils. spacings in regular and staggered array patterns. Due to the increased device miniaturization, the impact that device interconnects have on device performance and device cost has also become a larger factor in package development. Device interconnects, due to their increase in length in order to package complex devices and connect these devices to surrounding circuitry, tend to have an increasingly negative impact on the package performance. For longer and more robust metal interconnects, the parasitic capacitance and resistance of the metal interconnection increase, which degrades the chip performance significantly. Of particular concern in this respect is the voltage drop along power and ground buses and the RC delay that is introduced in the critical signal paths. In many cases the requirements that are placed on metal interconnects results in conflicting performance impacts. For instance, attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires. It is therefore the trend in the industry to look for and apply metals for the interconnects that have low electrical resistance, such as copper, while at the same time using materials that have low dielectric materials for insulation between interconnecting lines.
One of the more recent developments that is aimed at increasing the Input-Output (I/O) capabilities is the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on a semiconductor device, the bumps are interconnected directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. This technology can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger while more sophisticated substrates can be used that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and TCE (Temperature Coefficient of Expansion) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
In general, Chip-On-Board (COB) techniques are used to attach semiconductor die to a printed circuit board, these techniques include the technical disciplines of flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or to another substrate. A flip chip is a semiconductor chip that has a pattern or arrays of terminals that is spaced around an active surface of the flip chip that allows for face down mounting of the flip chip to a substrate.
Generally, the flip chip active surface has one of the following electrical connectors: BGA (wherein an array of minute solder balls is disposed on the surface of the flip chip that attaches to the substrate); Slightly Larger than Integrated Circuit Carrier (SLICC) (which is similar to the BGA but having a smaller solder ball pitch and diameter than the BGA); a Pin Grid Array (PGA) (wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board so that precise connection can be made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror image of the recesses on the printed circuit board. After insertion, soldering the pins in place generally bonds the flip chip.
A Prior Art method of packaging a BGA chip is shown in FIG. 1. The BGA chip 11 is mounted in a cavity 18 that is provided in the surface of a BGA substrate or a substrate 10, substrate 10 has a surface that is electrically conductive. The BGA chip 11 is centered with respect to the substrate 10, whereby the contact points of the semiconductor device 11 are closely spaced around the periphery of the die 11. Cavity 18 is provided in the substrate 10 for the mounting of the Integrated Circuit (IC) chip 11. The top surface of the IC chip 11 is in close physical contact with the substrate 10 via a thin adhesive layer 15, typically of thermally conductive epoxy, that is deposited over the top surface of cavity 18. The IC die 11 is attached to the substrate 10 by means of this layer 15, providing a path of heat conductivity between the semiconductor die. 11 and the substrate 10. The adhesive layer 15 is cured after the IC die 11 has been inserted into cavity 18. The contact points of the die 11 are conductively bonded, using wire-bonding techniques, to the substrate layer 19.
The bond wires 12 are shown here as applied for the connection of the IC die 11 to a top layer 13 of an interconnect substrate 19. The interconnect substrate 19 can contain multiple layers of interconnect lines and contact pads. The interconnect substrate 19 is connected to the underlying substrate 10 by means of layer 16, which is typically a layer of adhesive material. This establishes the necessary mechanical support for the wire bonding operation. The interconnect substrate 19 can further contain a mechanical stiffener to provide rigidity to the interconnect substrate 19. The upper layer of the interconnect substrate 19 contains (metal, for instance copper) traces 13 to which contact balls (not shown in FIG. 1) can be connected for further interconnects to surrounding circuitry or functional elements. Wires 12 provide a wire bond connection between contact points on the surface of the IC die 11 and copper traces 14 that are part of the interconnect substrate 19. For the connection of the upper layer of the interconnect substrate 19 to connecting solder balls, a solder mask layer (not shown in FIG. 1) with openings is deposited over the surface of the substrate layer 19. The openings that are created in the solder mask provide solder connections between the metal traces 13 and the contact balls.
FIG. 1 also shows how the IC die 11 is encapsulated using an encapsulation material that is syringe dispensed to surround the die 11 forming the encapsulation layer 17. It must be noted that this layer not only surrounds the IC die 11, but also covers the bond wires 12. The encapsulation layer 17 is cured after injection.
The Prior Art package that is shown in FIG. 1 is of a somewhat elaborate design in that it has a heat sink in which a cavity is provided for the insertion of a semiconductor die, a substrate that may contain multiple interconnect layers and methods of encapsulating the mounted semiconductor die. Simpler methods for mounting a semiconductor die can be used whereby the die is mounted directly on the surface of a Printed Circuit Board (PCB) while layers of metal interconnect within the PCB are used to connect the I/O connections of the mounted die to surrounding circuitry. In most applications of this kind, the die is still provided with contact balls, these contact balls rest directly on the surface of the PCB and are connected to electrical points of contact that are opened in the surface of the PCB.
One such application is shown in FIG. 2, where a semiconductor die 46 is surface mounted on a Printed Circuit Board (PCB) 40. A layer 42 of top metal is provided on the surface of the PCB 40, the die 46 is connected to the layer 42 of top metal via the BGA contact balls 44. It is clear that the top layer 42 of metal is connected to one or more layers of interconnect metal that are within the body of the PCB 40, the top layer of metal 42 can be a layer of metal that has been deposited on the surface of the PCB and patterned and etched to provide to desired interconnect pattern on the surface of the PCB 40. It is also possible to use metal pads that are part of the top layer of metal within the PCB and that have been exposed for interconnect to the semiconductor die 46. The die 46 contains mostly silicon while numerous other materials may have been added to the silicon die in order to create a functional semiconductor device. One of the more serious problems that is encountered in the method that is shown in FIG. 2 is that there is a significant thermal mismatch between the PCB 40 and the silicon that is predominantly contained in die 46. As already pointed out, a severe mismatch in the TCE (Temperature Coefficient of Expansion) between the silicon die and the underlying PCB causes severe solder bump fatigue during the unavoidable thermal cycles to which the package is subjected. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints, this can lead to joint breakage caused by solder fatigue from temperature cycling operations. Conventional methods apply a thermal compliant material on the surface of the silicon die in order to alleviate the effect of thermal stress.
This process however incurs significant manufacturing cost and is therefore to be avoided. The invention addresses a method that allows for the elimination of thermal stress between the mounted die and the underlying PCB, while not incurring the expense of providing a layer of thermal compliant material on the surface of the die that conventionally is used to alleviate thermal stress.
Numerous other examples of die attachment and methods of packaging semiconductor die are readily available in the literature of the art. Some further detail will be provided relating to these various methods in the below referenced and related US Patents.
U.S. Pat. No. 6,031,282 (Jones et al.) shows an IC package with an elastomer on a PCB and die pads. This Patent shown an example of Prior Art packages wherein the semiconductor die is mounted inside a lower part of the package, outer leads run from the die to connection points on the surface of a FCB on which the package is mounted. The die is protected and the package is closed by an upper part of the package. As an alternate example of Prior Art packaging, this Patent shows a BGA package that strongly resembles the previously cited Prior Art example of FIG. 1. In this case, the semiconductor die is mounted on the surface of an underlying PCB. The Patent of this invention provides for a Chip Scale Package wherein the package size is equivalent to the size of the die that is mounted in the package, providing advantages of packaging high density semiconductor devices. This package does not make use of Elastomer as an isolation material.
U.S. Pat. No. 6,041,495 (Yoon et al.) shows a PCB with an elastomer and chip mount. This Patent shows a number of Prior Art application using PCB""s for the mounting of BGA devices, these devices are mounted either on a top or a bottom surface of the PCB. This Patent makes use of mounting a semiconductor die on the surface of the PCB, a metal plate is used as part of the package. This Patent also makes use of a flexible circuit board for the mounting of semiconductor devices, this application uses polyimide tape that is attached to the flexible circuit board.
U.S. Pat. No. 5,889,652 (Turturro) shows a PCB and a substrate with an elastomer therebetween. This patent differentiates between a contact portion of the package and a bond portion. The two (contact and bond) portions of the package are interconnected via a flexible portion (elastomer). This allows relative movement between the package (on which the die is mounted) and the PCB, in this manner reducing thermal and mechanical stress on the solder joints.
U.S. Pat. No. 5,990,545 (Schueller et al.) shows a SCBGA with a PCB and direct chip attach with an elastomer to compensate for the thermal mismatch of the PCB and the die. A nonpolymer layer or support structure is positioned between the semiconductor die and the underlying substrate reducing effects of thermal stress.
Distefano et al., xe2x80x9cDesigning a Modular Chip Scale Package Assembly Linexe2x80x9d, Circuit Assembly, Mar. 1977, (pages not numbered). This article focuses on the Chip Scale Package (CSP) and provides methods and procedures for relatively easy assembly of CSP""s.
A principle objective of the invention is to eliminate thermal stress between a mounted semiconductor die and an underlying Printed Circuit Board.
Another objective of the invention is to provide a cost effective method to eliminate thermal stress between a mounted semiconductor die and the underlying Printed Circuit Board.
Yet another objective of the invention is to provide a method that allows for direct die attachment to a surface of a Printed Circuit Board without incurring negative results of thermal mismatch between the semiconductor die and the Printed Circuit Board.
In accordance with the objectives of the invention a new method is provided to mount a semiconductor on the surface of a Printed Circuit Board. A layer of Elastomer is deposited on the surface of the PCB, this layer of Elastomer makes the PCB into a thermally compliant PCB such that the thermal mismatch between the PCB and the semiconductor die that is mounted on the PCB is sharply reduced. Openings are created in the layer of Elastomer and electrical interfaces are created such that the PCB can be connected to the semiconductor die that is mounted on the PCB.